Soc and ASIC Jobs Jobs - Find the most exclusive Soc and ASIC Jobs in India

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Senior ASIC/SoC Design Engineer (Front end) Jobs in Chennai

Senior ASIC/SoC Design Engineer (Front end) openings with Product based MNC in Chennai Senior Design Engineer, Design Engineer (Front end) Responsibilities Work with digital designer and verification engineers to design and test digital blocks and interface modules. Writing of verification...

Updated: 2012-May-23 05:05 PM

Industry: IT ProductsRole: Senior Design Engineer, Design Engineer (Front end)

Experience Level: 5.0 to 9.0 yrsLocation: (India)

Keywords: ASIC SOC

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C/C++, Soc and ASIC, XML, TCL, Perl, Lead Engineer – Genesis for electronic design automation, Esteemed Client of Roland & Associates, Noida Mail your resume to seemant@roljobs.com

The candidate should have 4-5 years experience in developing C/C++ based core/application software for popular tools in the EDA industry. Knowledge of VHDL, Verilog would be required. Working knowledge of XML, TCL, and Perl is a plus.The candidate will be responsible for Coding (Enhancements Bug...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: Lead Engineer – Genesis for electronic design automation

Experience Level: 4.0 to 5.0 yrsLocation: Noida (India)

Keywords: C/C++ Soc and ASIC XML TCL Perl algorithm analysis and data structures

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ASIC/SOC Verification Jobs India & USA

Expereince: 2-10 Years Location: India /USA Education:B.E/B.Tech/M.E/M.Tech/M.S Skill: Strong is ASIC Verification SOC Verification with Verilog OR IP Verification with "System Verilog" Verification Methodology like OVM/VMM/UVM

Updated: 2012-May-24 02:39 PM

Industry: SemiconductorRole: ASIC Verification Engineer

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore Hyderabad Vizag Noida (United States)

Keywords: ASIC Verification System verilog OVM/VMM

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Senior IC Design Engineer Jobs in Chennai

Senior IC Design Engineer Jobs in Chennai Note: Ready to join in 30 days Senior Design Engineer, Design Engineer (Front end) Responsibilities Work with digital designer and verification engineers to design and test digital blocks and interface modules. Writing of verification plans, contribute...

Updated: 2012-May-22 05:12 PM

Industry: IT Products, Hardware, Semiconductor, IT ServicesRole: design engineer

Experience Level: 6.0 to 10.0 yrsLocation: (India)

Keywords: ASIC SOC

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Physical Design, RTL Design, DFT, Design For Testability, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, Physical Design Professionals, San Jose San Diego

Verification Professionals Jobs JD Positions : Physical Design Professionals Experience: 3 -8 Years Location : San Jose / San Deigo (US) Skills :synthesis and STA, Static timing analysis,Synopsys ICC, ASIC Implementation, P&R, Cadence encounter, RTL to GDS, RTL to GDSII. Mail your CV to...

Updated: 2012-Mar-29 06:01 PM

Industry: SemiconductorRole: Physical Design Professionals

Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)

Keywords: Physical Design RTL Design DFT Design For Testability ASIC Backend SOC encounter Magma Talus IC Compiler floor planning PnR Placement and routing synthesis and STA Static timing analysis Synopsys ICC ASIC Implementation P&R Cadence encounter RTL to GDS RTL to GDSII.

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Jobs Lead ASIC Design Engineer

Market leader in VLSI Industry Hiring Lead ASIC Design Engineer with 25+ Salary Minimum 10 years in ASIC front end design Should lead a minimum of 30 Members. Working with reputed Semiconductor MNC Professionals interested can mail me to : lijith@roljobs.com Regards Lijith V V Mail :...

Updated: 2012-Mar-19 05:09 PM

Industry: SemiconductorRole: Lead ASIC Design Engineer

Experience Level: 10.0 to 19.0 yrsLocation: (India)

Keywords: ASIC Design SoC design RTL design Digital Design

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Mar-20 05:49 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Soc Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: Soc Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: Soc Prototyping FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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Senior Design Engineer/ Design Engineer (Front end) jobs for Chennai location.

Senior Design Engineer/ Design Engineer (Front end) jobs for Chennai location. Experience : 6-8 years Location : Chennai Qualification : Bachelors/Master in engineering Job description : Mandatory Skills: Knowledge of typical ASIC/SoC design/verification flow and tools Knowledge and experience...

Updated: 2012-May-22 05:42 PM

Industry: IT ProductsRole: Senior Design Engineer/ Design Engineer (Front end)

Experience Level: 6.0 to 12.0 yrsLocation: Chennai (India)

Keywords: SoC ASIC Verilog

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ASIC Verification jobs with excellent salary in Bangalore

Description : • Proficiency in one or more HVL's a must (System Verilog,Specman, C++, Vera, e, System C, test builder). • Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA

Updated: 2012-May-16 03:55 PM

Industry: SemiconductorRole: ASIC Verification jobs with excellent salary in Bangalore

Experience Level: 3.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification system verilog specman SOC verification system c

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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