Place and Route Jobs Jobs - Find the most exclusive Place and Route Jobs in India

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PNR opening with Product Based MNC (Semiconductor Domain) @ Greater Noida.

The incubent will be responsible for Physical Implementation of Imaging SoC"s. Primarily - BE (Floor Plan, PNR, Clock-tree, TA, IRdrop, Sign-ff, Mask finishing) and participate in FE (synthèses, TA, Formal Verification, Sign-off, Hand-off)

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: PNR

Experience Level: 1.0 to 2.0 yrsLocation: Greater Noida (India)

Keywords: place and route (PNR) Cadence Magma Synopsys PNR tools SoC

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Opening for PNR with Product Based MNC Semiconductor @ Greater Noida.

The incubent will be responsible for Physical Implementation of Imaging SoC"s. Primarily - BE (Floor Plan, PNR, Clock-tree, TA, IRdrop, Sign-ff, Mask finishing) and participate in FE (synthèses, TA, Formal Verification, Sign-off, Hand-off)

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: PNR

Experience Level: 1.0 to 2.0 yrsLocation: Greater Noida (India)

Keywords: place and route (PNR) Cadence Magma Synopsys PNR tools SoC Signoff floor plan

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ASIC Physical Design Jobs in Bangalore/Hyderabad/Noida/Vizag

Expereince: 2-8 Years Education:B.E/B.Tech/M.E/M.Tech Location: Bangalore/Hyderabad/Vizag/Noida Skills: Strong in ASIC Physical Design Floor planning,Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route,Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR...

Updated: 2012-May-04 03:28 PM

Industry: SemiconductorRole: Physical Design Engineer/Lead

Experience Level: 2.0 to 8.0 yrsLocation: Bangalore Hyderabad Vizag Noida (India)

Keywords: Floor planning Synthesis STA IO Ring Penetration Power Analysis Place & Route Design

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Placement and Routing Jobs

Job Title : Placement and Routing Engineer Experience : 1 - 15 Job Location : Bangalore, Ahmedabad, Pune, Chennai, Hyderabad Position exist at all levels. Skills : Physical Design, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, Synthesis and...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: Placement and Routing Engineer

Experience Level: 1.0 to 15.0 yrsLocation: Chennai (India)

Keywords: Physical Design IC Compiler SOC encounter ASIC Backend Magma Talus Floor Planning P&R Placement and Routing Synthesis and STA Static Timing Anlysis Cadence encounter RTL to GDS RTL to GDSII

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Physical Design, RTL Design, DFT, Design For Testability, ASIC Backend, SOC encounter, Magma Talus, IC Compiler, floor planning, PnR, Placement and routing, Physical Design Professionals, San Jose San Diego

Verification Professionals Jobs JD Positions : Physical Design Professionals Experience: 3 -8 Years Location : San Jose / San Deigo (US) Skills :synthesis and STA, Static timing analysis,Synopsys ICC, ASIC Implementation, P&R, Cadence encounter, RTL to GDS, RTL to GDSII. Mail your CV to...

Updated: 2012-Mar-29 06:01 PM

Industry: SemiconductorRole: Physical Design Professionals

Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)

Keywords: Physical Design RTL Design DFT Design For Testability ASIC Backend SOC encounter Magma Talus IC Compiler floor planning PnR Placement and routing synthesis and STA Static timing analysis Synopsys ICC ASIC Implementation P&R Cadence encounter RTL to GDS RTL to GDSII.

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Jobs for Device Driver development

CISCO experience and familiarity with IOS is a plus. Good at "C" programming and data structures

Updated: 2012-May-16 04:34 PM

Industry: IT ServicesRole: SE/ SSE (Developer)

Experience Level: 3.0 to 6.0 yrsLocation: Bangalore (India)

Keywords: MPLS Routing Protocols OSPF/ ISIS

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Product Manager Jobs in Pune for a Product Based MNC.

Product Manager Jobs in Pune for a Product Based MNC. Job Title : Product Manager Experience : 6-10 Years. Location : Pune Qualification :BE/BTECH/ME/MTECH/MCA Skills Required : Minimum of 6 years of experience in product delivery processes and interaction with multiple...

Updated: 2012-Apr-30 06:44 PM

Industry: Communications and NetworkingRole: Product Manager

Experience Level: 6.0 to 10.0 yrsLocation: Pune (India)

Keywords: wireless Swichingrouting LANWAN

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Jobs for Driver Development

Proficient in System Software Operating System Concepts (Linux/ Vxworks/ RTOS). CISCO experience and familiarity with IOS is a plus. Good at "C" programming and data stru ctures.

Updated: 2012-May-15 04:42 PM

Industry: Industrial Products/Heavy MachineryRole: Driver development -SE/ SSE (Developer)

Experience Level: 3.0 to 6.0 yrsLocation: Bangalore (India)

Keywords: Driver development Broadcom SDK MPLS and/or Routing Protocols

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Jobs for Protocol Testing

Routing Switching. Experience with configuring CISCO catalyst Series switches (Cat 4k/ Cat 6k) Testing tools like Ixia, Spirent, Adtech etc.

Updated: 2012-May-14 03:25 PM

Industry: IT ServicesRole: SSE (Protocol Testing)

Experience Level: 4.0 to 6.0 yrsLocation: Bangalore (India)

Keywords: Routing & Switching. VLAN Switching Ixia Spirent Adtech

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Jobs for Driver Development

Experience in Layer 2 Switching, Firewall and L3 routing. Experience in MPLS and/or Routing Protocols such as OSPF/ ISIS is a plus. Proficient in System Software Operating System Concepts (Linux/ Vxworks/ RTOS).

Updated: 2012-May-14 03:15 PM

Industry: IT ServicesRole: Developer

Experience Level: 3.0 to 6.0 yrsLocation: Bangalore (India)

Keywords: Driver development Layer 2 Switching MPLS and/or Routing Protocols

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Jobs for Catia V5 ( Engine Periphery Design ) @ Bangalore mail your resume to rashmi@roljobs.com

Design and Development of Engine Periphery parts that include Pipes, Hoses, Engine Mounts, Heat Shields, Brackets.

Updated: 2012-Mar-09 01:02 AM

Industry: AutomobileRole: Engine Periphery Design

Experience Level: 6.0 to 9.0 yrsLocation: Bangalore (India)

Keywords: Engine Periphery Design Catia V5 Piping piping and tubing routing design

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Physical Design

Position: Physical Design Engineer Location: Bangalore Experience : 1.5-6.0 Years Qualification : B.E/B.Tech/M.Tech Job Duties Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm 65nm) Work on all aspects of physical design including synthesis,...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: Physical Design openings in Bangalore

Experience Level: 1.5 to 6.0 yrsLocation: Bangalore (India)

Keywords: Physical design Backend design SOC encounter Netlist to GDS Placement & Routing

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Hiring Physical design professionals -US based MNC in Bangalore

· Implementation of multimillion gate SoC designs in cutting edge process technologies (28nm, 45nm 65nm) · Work on all aspects of physical design including synthesis, floor planning, place and route, clock distribution, IP integration, extraction, timing closure, power and signal integrity...

Updated: 2012-May-05 11:16 AM

Industry: SemiconductorRole: Hiring Physical design professionals -US based MNC in Bangalore

Experience Level: 2.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: Physical design SOC encounter backend design IC compiler placement & routing netlist to GDS

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Physical design professionals required-US based MNC

Detailed Description of the Job Profile: 6-7 Yr of experience in doing hands on physical design Preferred Synopsys ICC, Magma Talus on at least four project. Strong fundamentals on Physical design including Floor plan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing...

Updated: 2012-Apr-21 01:10 PM

Industry: SemiconductorRole: Physical design professionals required-US based MNC

Experience Level: 6.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: physical design SOC encounter backend design IC compiler Placement and routing Netlist to GDS

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Physical Design Engineers Jobs openings in Bangalore/Noida/Hyderabad

Skills Required:- Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis IR drop analysis, Physical verification, Signal Integrity, Low Power design.

Updated: 2012-Apr-21 10:41 AM

Industry: SemiconductorRole: Physical design Engineer

Experience Level: 2.0 to 15.0 yrsLocation: Bangalore Noida,Hyderabad ,Vizag (India)

Keywords: Physical design SOC encounter backend design IC compiler placement & routing timing analysis

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Physical design professionals required- US Based MNC

Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis IR drop analysis, Physical verification, Signal Integrity, Low Power design.

Updated: 2012-Apr-19 06:25 PM

Industry: SemiconductorRole: Physical design

Experience Level: 2.0 to 14.0 yrsLocation: Bangalore Noida,Hyderabad (India)

Keywords: Physical design SOC encounter backend design IC compiler placement & routing timing analysis

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Jobs for technical Support Engineer@Bangalore

Excellent Opening for Technical Support Engineer Qualifications(Please apply who can join in 30 days) Candidates with 1- 4 years of experience. Bachelors/Masters Degree on Telecommunications Engineering, Electronic Engineering or Computer Science or related field or equivalent experience. CCNP...

Updated: 2012-Mar-09 01:02 AM

Industry: Telecom/ISPRole: Technical Support Engineer

Experience Level: 2.0 to 3.0 yrsLocation: (India)

Keywords: L2/L3(Networking Protocols) routing protocols (e.g. OSPF BGP IS-IS) proficient in scripting (tcl/perl)Proficiency in Linux and Windows troubleshooting ability FTP HTTP

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US Jobs for Physical Design Engineers

System Verilog Jobs JD Positions : Exist at all levels Experience: 3-8 Years Location : San Jose/San Deigo (CA) Skills : System verilog, Vera, OVM, VMM, UVM Mail your CV to priyank.srivastava@roljobs.com with the following details current ctc : expected ctc : Notice Period: Location Preferred:...

Updated: 2012-Apr-30 03:45 PM

Industry: SemiconductorRole: Physical Design Professionals

Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)

Keywords: Physical Design RTL Design DFT Design For Testability ASIC Backend SOC encounter Magma Talus IC Compiler floor planning PnR Placement and routing synthesis and STA Static timing analysis Synopsys ICC ASIC Implementation P&R Cadence encounter RTL to GDS RTL to GDSII.

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US Offer for Physical Design Engineers

System Verilog Jobs JD Positions : Exist at all levels Experience: 3-8 Years Location : San Jose/San Deigo (CA) Skills : System verilog, Vera, OVM, VMM, UVM Mail your CV to priyank.srivastava@roljobs.com with the following details current ctc : expected ctc : Notice Period: Location Preferred:...

Updated: 2012-Apr-30 03:45 PM

Industry: SemiconductorRole: Physical Design Professionals

Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)

Keywords: Physical Design RTL Design DFT Design For Testability ASIC Backend SOC encounter Magma Talus IC Compiler floor planning PnR Placement and routing synthesis and STA Static timing analysis Synopsys ICC ASIC Implementation P&R Cadence encounter RTL to GDS RTL to GDSII.

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Direct US opportunity for Physical Design Engineers

System Verilog Jobs JD Positions : Exist at all levels Experience: 3-8 Years Location : San Jose/San Deigo (CA) Skills : System verilog, Vera, OVM, VMM, UVM Mail your CV to priyank.srivastava@roljobs.com with the following details current ctc : expected ctc : Notice Period: Location Preferred:...

Updated: 2012-Apr-30 03:45 PM

Industry: SemiconductorRole: Physical Design Professionals

Experience Level: 3.0 to 8.0 yrsLocation: San Jose San Diego (US)

Keywords: Physical Design RTL Design DFT Design For Testability ASIC Backend SOC encounter Magma Talus IC Compiler floor planning PnR Placement and routing synthesis and STA Static timing analysis Synopsys ICC ASIC Implementation P&R Cadence encounter RTL to GDS RTL to GDSII.

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