Calibre drc Jobs Jobs - Find the most exclusive Calibre drc Jobs in India

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Project Manager Openings for a Product Based MNC @ Bangalore : - Salary 30+ Lakhs

Responsible for block level and as well as chip level layout including verification. Responsible for ownership and signoff for the tapeout of the products.

Updated: 2012-Mar-28 05:50 PM

Industry: SemiconductorRole: Analog Layout Manager

Experience Level: 11.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Analog Layout Virtuoso Analog Signal DRC

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Project Lead Openings for Analog Layout Engineers( 11+ Years) :- Salary 22+ Lakhs

Responsible for block level and as well as chip level layout including verification. Responsible for ownership and signoff for the tapeout of the products.

Updated: 2012-Mar-28 05:17 PM

Industry: SemiconductorRole: Sr.Analog Layout Engineer

Experience Level: 11.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Analog Layout Virtuoso Analog Signal DRC

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Project Lead Openings for Analog Layout Engineers(11 @ Bangalore : - Salary 22+ Lakhs

Responsible for block level and as well as chip level layout including verification. Responsible for ownership and signoff for the tapeout of the products.

Updated: 2012-Mar-28 05:15 PM

Industry: SemiconductorRole: Sr.Analog Layout Engineer

Experience Level: 11.0 to 15.0 yrsLocation: Bangalore (India)

Keywords: Analog Layout Virtuoso Analog Signal DRC

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Standard cell library layout

Job description: Job Title: Engineer,Standard Cell Library Layout Design Location : Bangalore Experience : 4-6 Years Qualification:B.E / B.Tech in Electronics Engineering General Description:- *Should have hands-on experience in layout design of standard cells and physical verification checks....

Updated: 2012-Apr-19 12:57 PM

Industry: SemiconductorRole: Standard cell Openings in Bangalore,Noida and Hyderabad

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore Hyderabad Noida (India)

Keywords: Standard cell Calibre Hercules and Assura standard cell layout design standard cell characterization.

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Standard Cell Layout Design / Memory Layout Design / IO Layout Design Jobs opernings in Bangalore & Noida

1)Position: Standard Cell Layout Design Experience: 4 to 8 years Location: Noida Bangalore Qualification: B.E/B.Tech/M.E/M.Tech Skill set : Exposure to Calibre, Hercules and Assura Strong basics in process technology, fabrication techniques Strong expertise in standard cell layout design and...

Updated: 2012-Apr-20 06:51 PM

Industry: ITES / BPO / Customer Service, SemiconductorRole: Layout Engineer

Experience Level: 2.0 to 9.0 yrsLocation: Bangalore Noida (India)

Keywords: Calibre Hercules "IO Layout" "Memory layout" "Standard cell layout"

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Layout Engineer Jobs

Position: Standard Cell Layout Design Experience: 4 to 8 years Location: Noida Bangalore Qualification: B.E/B.Tech/M.E/M.Tech Skill set : Exposure to Calibre, Hercules and Assura Strong basics in process technology, fabrication techniques Strong expertise in standard cell layout design and...

Updated: 2012-Apr-19 08:04 PM

Industry: ITES / BPO / Customer Service, SemiconductorRole: Layout Engineer

Experience Level: 2.0 to 9.0 yrsLocation: (India)

Keywords: Calibre Hercules "IO Layout" "Memory layout" "Standard cell layout"

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Layout Design(Standard Cell / Memory Layout / IO Layout )Jobs at Bangalore & Noida

1)Position: Standard Cell Layout Design Experience: 4 to 8 years Work Location: Noida Bangalore Qualification: B.E/B.Tech/M.E/M.Tech Skill set : Exposure to Calibre, Hercules and Assura Strong basics in process technology, fabrication techniques Strong expertise in standard cell layout design...

Updated: 2012-Apr-25 03:51 PM

Industry: SemiconductorRole: Layout Design (Standard Cell / Memory Layout / IO Layout )

Experience Level: 2.0 to 9.0 yrsLocation: Bangalore Noida (India)

Keywords: "IO Layout" "Memory layout" "Standard cell layout" Calibre HerculesAssura

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Memory layout Jobs@ Bangalore & Noida

Role: Memory Layout Design Strong expertise in SRAM/ DRAM and memory compilers Responsibilities: Should be able to work on memory Layout designs, physical verification using industry standard tools.

Updated: 2012-Apr-25 03:30 PM

Industry: IT ServicesRole: Memory cell layout design

Experience Level: 4.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: Memory layout design layout design SRAM DRAM Calibre Assura Hercules

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DFT Jobs

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Bangalore (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Jobs

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Noida (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Jobs

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Hyderabad (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Jobs

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Visakhapatnam (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Opportunities

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Bangalore (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Opportunities

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Noida (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Opportunities

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Hyderabad (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Opportunities

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Visakhapatnam (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Vacancies

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Bangalore (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Vacancies

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Noida (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Vacancies

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Hyderabad (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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DFT Vacancies

Job Title : DFT Engineer Experience : 1 – 15 Years Position exist at all levels Job Location : Bangalore, Visakhapatnam, Noida Hyderabad Mandatory Skills : DFT,Design For Testability,ATPG,JTAG,BIST,Built In Self Test,PBIST,MBIST,LBIST,FastScan,Tetramax Mail your resume to bhargavi@roljobs.com...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: DFT Engineer

Location: Visakhapatnam (India)

Keywords: DFT Design For Testability ATPG JTAG BIST Built In Self Test PBIST MBIST LBIST FastScan Tetramax scan failures/blockage DFT DRC failures timing failures signature analysis

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