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VLSI Jobs: ASIC design (RTL) in Bangalore.

VLSI Jobs: ASIC design (RTL) in Bangalore. About our Client : Us based product development company. Requirement : Experience :1 -4 Years Location :Bangalore Education:B.Tech/M.Tech(NIT/IIT) Position : Design Engineer Responsibilities: The position will be responsible for performing one of the...

Updated: 2012-Apr-30 06:32 PM

Role: ASIC Designer

Experience Level: 1.0 to 4.0 yrsLocation: (India)

Keywords: ASIC RTL

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Apr-16 04:08 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Prototyping jobs in Pune

Job Description Design and coding using VHDL FPGA prototyping which may require partitioning the core on two or more FPGAs. FPGA simulation and verification Exposure to a range of FPGA design tools (preferably Synopsys Certify and Synplify, Xilinx ISE) Multi-FPGA design partitioning Experience of...

Updated: 2012-Mar-20 05:49 PM

Industry: SemiconductorsRole: ASIC Prototyping

Experience Level: 2.0 to 5.0 yrsLocation: Pune (India)

Keywords: ASIC FPGA "Synopsys Certify" Synplify "Xilinx ISE" Verilog VHDL FPGA PCI "PCI Express" "PCI-E" “FPGA prototype” “FPGA Prototyping” “ASIC Prototyping” “Soc Prototyping”

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ASIC Design Engineer Jobs in Hyderbad - shekar@roljobs.com

Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge of FPGA. Exposure in STA. Must have completed at least one front-end design cycle. Should definitely have Synthesis (Synopsys DC) and...

Updated: 2012-Mar-09 01:02 AM

Industry: Communications and Networking, Hardware, IT ProductsRole: ASIC Design Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Hyderabad (India)

Keywords: ASIC VHDL verilog

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ASIC Design Engineer Jobs in Bangalore - shekar@roljobs.com

Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge of FPGA. Exposure in STA. Must have completed at least one front-end design cycle. Should definitely have Synthesis (Synopsys DC) and...

Updated: 2012-Mar-09 01:02 AM

Industry: Communications and Networking, Hardware, IT ProductsRole: ASIC Design Engineer

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: ASIC VHDL verilog

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ASIC VERIFICATION

Senior Engineer Functional Verification(Digital) Experience - 3-8 years Location: Bangalore Hyderabad Educational Qualification: B.E/B.TECH/M.E/M. TECH -Full Chip verification of a SOC or a non-SOC in a product company, or as a contractor -Start to End Responsibility for verification of a block...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: Openings for Verification (Digital)- Bangalore and Hyderabad

Experience Level: 2.0 to 8.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification Front end design system verilog specman

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ASIC Verification Engineer Jobs in Hyderbad - shekar@roljobs.com

Job Description Hands On experience in complex ASIC Design Verification, direct experience in SOC or Processor is preferred. Must have excellent knowledge of ASIC Design Flow. Experience with C C++ Experience in developing complex test bench/model in System verilog. Excellent debug skills in...

Updated: 2012-Mar-09 01:02 AM

Industry: Communications and Networking, Hardware, IT ProductsRole: ASIC Verification

Experience Level: 4.0 to 7.0 yrsLocation: Hyderabad (India)

Keywords: ASIC Verification VHDL verilog

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ASIC Verification Engineer Jobs in Bangalore - shekar@roljobs.com

Job Description Hands On experience in complex ASIC Design Verification, direct experience in SOC or Processor is preferred. Must have excellent knowledge of ASIC Design Flow. Experience with C C++ Experience in developing complex test bench/model in System verilog. Excellent debug skills in...

Updated: 2012-Mar-09 01:02 AM

Industry: Communications and Networking, Hardware, IT ProductsRole: ASIC Verification

Experience Level: 4.0 to 7.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verification VHDL verilog

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Job :ASIC/FPGA Design(Digital) in Bangalore.

Job :ASIC/FPGA Design(Digital) in Bangalore. Experience: 4-6 Yrs Location: Bangalore designation :Sr. Engineer/Tech Lead Educational Qualification: B.E., B.TECH, M.E. M. TECH Detailed Description of the Job Profile : This person will be leading a team of junior engineers. He will be involved...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: Sr. Engineer/Tech Lead

Experience Level: 4.0 to 6.0 yrsLocation: (India)

Keywords: ASIC Desiner Ethernet

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Semiconductor Jobs @ Bangalore - ASIC Verification Engineer (System Verilog/Specman/HVL/SystemC/Vera/OVM/VMM/UVM)

Hi, we have openings for ASIC Verification engineers in Bangalore, Hyderabad ,Chennai Noida Location. Job Description: Position: Verification Engineer Years of Experience: 3 to 10 Years Education: BE/B.Tech/ME/M.Tech/MS Job Location: Bangalore

Updated: 2012-May-17 06:49 PM

Industry: SemiconductorRole: ASIC Verification Engineer

Experience Level: 3.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: ASIC System Verilog Specman OVM VMM UVM SystemC Vera HVLs

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ASIC Backend Jobs in Bangalore & Hyderabad

Job Title : Physical Design Engineer /Lead Engineer/Manager Experience : 3 - 12 Years Job Location : Bangalore, Hyderabad

Updated: 2012-Mar-13 07:00 PM

Role: ASIC Backend Engineer

Experience Level: 3.0 to 12.0 yrsLocation: Bangalore Hyderabad (India)

Keywords: "ASIC Backend"

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ASIC Design Engineer

ASIC Design Engineer Qualification: B.Tech/B.E (ECE/EE)/M.S/M.Tech (VLSI/Digital Electronics) Experience: 2-10 yrs Location: Bangalore Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: ASIC Design Engineer

Experience Level: 2.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verilog VHDL FPGA STA Synthesis Simulation PCIe PCI/-X Ethernet AMBA AHB AXI USB

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ASIC Design Engineer

ASIC Design Engineer Qualification: B.Tech/B.E (ECE/EE)/M.S/M.Tech (VLSI/Digital Electronics) Experience: 2-10 yrs Location: Bangalore Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: ASIC Design Engineer

Experience Level: 2.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verilog VHDL FPGA STA Synthesis Simulation PCIe PCI/-X Ethernet AMBA AHB AXI USB

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ASIC Design Engineer

ASIC Design Engineer Qualification: B.Tech/B.E (ECE/EE)/M.S/M.Tech (VLSI/Digital Electronics) Experience: 2-10 yrs Location: Bangalore Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: ASIC Design Engineer

Experience Level: 2.0 to 10.0 yrsLocation: Bangalore (India)

Keywords: ASIC Verilog VHDL FPGA STA Synthesis Simulation PCIe PCI/-X Ethernet AMBA AHB AXI USB

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ASIC Design Engineer

ASIC Design Engineer Qualification: B.Tech/B.E (ECE/EE)/M.S/M.Tech (VLSI/Digital Electronics) Experience: 2-10 yrs Location: Bangalore Job Description Verilog, VHDL knowledge is essential. Knowledge of an Operating System: UNIX / LINUX /windows XP. Knowledge of C and PERL is preferred. Knowledge...

Updated: 2012-Mar-09 01:02 AM

Industry: SemiconductorRole: ASIC Design Engineer

Experience Level: 2.0 to 10.0 yrsLocation: Bangalore (India)

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