Generating, verifying and debugging manufacturing test designs and firmware for new Flash-based FPGA families.

Improving, extending and porting existing manufacturing test designs to all FPGA family members.

Support Failure Analysis and help with silicon debug and ramp up.

Test specification, plan, and documentation

Cross-functional team interfacing and collaboration in all activities

BS or MS in EE and a minimum of 6 years of experience in Design for Test or Test development

Hands-on experience with Programming/software in C/C++

Firmware Development: 8051 and ARM are preferred

Hands-on experience with Verilog Hardware Description Language

• Behavioral, RTL and Gate Level coding, Programming Language Interface

Hands-on experience with at least 3 aspects of Logic Testing and Design for-Testability including:

• Fault Simulation Methodologies and tools such as TurboFault,

• Scan Design & ATPG (TetraMax, FastScan, DFTCompiler…)

• Test Generation,

• Signature Analysis,

• Memory BIST design with tools such as MBIST architect.

• Delay Faults

Exposure to ASIC/FPGA design flow and methodology is required

• HDL, synthesis, static timing analysis, constraining, Place & Route

Understanding of semiconductor technologies and related yield issues

Comfortable with Unix, Fluent in Perl and/or Shell scripting, agile with Make, and familiar with Revision Control (CVS, SVN, …)

Experience in Project Management is highly desired

Strong analytical and problem solving skills

Excellent communication, documentation and presentation skills.

Must have strong self learning ability, leadership, and enjoy working in teams

Professionals interested in exploring this opportunity, Can revert to aishwaraya@roljobs.com