Memory Design group at Bangalore is involved in design of all types of memory generators like SRAM generators, Register files, ROM generators etc.

Right from the spec definition to the test chip releases. The candidate’s role includes:

* Define and Improve   high speed and/or low power memory architectures

* Perform the bit cell evaluation and identify the read/write issues associated with it, 

* Write vectors and perform functional verification of memory 

* Timing/Power analysis and characterization

* Physical verification and DFM, DFY analysis

Personal Requirements:

Graduate /Post Graduate from a reputed  technical school or college degree

 Essential Technical Skills:

     * 2 – 4 years of relevant circuit design experience

    * Experience working with circuit simulation tools and techniques.

    * Experience working with Hercules/Calibre drc/lvs verification tools

    * Fundamental understanding of Design For Manufacturability (DFM)

    * Familiarity with Cadence Virtuoso (DFII, Opus) layout environment

Desirable Skills:

    * Circuit design  experience with memory compilers

    * Circuit/Layout experience with deep submicron technologies (0.13 or smaller)

    * Experience working with place & route chip design tools

    * Experience with other EDA tools such as design_compiler, Astro, Physical Compiler, PrimeTime, SoC Encounter

    * Programming or scripting experience

    * Coding, modifying, or reading DRC/LVS runsets

    * Basic scripting knowledge in Perl

Personal Skills:

    * Enthusiastic, self-motivated, flexible with strong inter-personal skills

    * High degree of initiative

    * Willingness and ability to contribute to process improvement initiatives

    * Good communication skills, oral and written

Package:

    * Competitive salary commensurate with experience

    * Equity in the form of Restricted Share Units

    * Annual bonus plan

    * Health, Life and Accident Insurance

    * Development opportunities