Location:Bangalore
Position:ASIC Verification Engineer-System Verilog
Qualification:B.E,M.E
Experience:5- 10 Years

Responsibilities include:

•     Define pre-silicon verification/test plan.

•     Execute verification plan using SystemVerilog/Verilog using both direct and Constrained Randomized verification methodology.

•     Create and debug test case both in RTL and Gate Level simulation environment.

•     Define and generate assertions and functional coverage points.

•     Automate verification environment using Scripts.

•     Create & analyze coverage metrics to ensure completeness.

REQUIREMENTS:

•     BSEE, MSEE desired

•     Minimum 5+ years of experience in ASIC design/verification

•     Must possess at least 3 years work experience with SystemVerilog for verification.

•     3+ years of experience in both RTL and gate level verification and debug.

•     Verification experience in the following product areas:

o     High speed serial link (PCI-E,  XAUI)

o     DDR2/DDR3 memory controller

o     High speed network or switching controller. .

Regards

Varsha Vijesh